:PROPERTIES: :ID: 291fc29e-4881-47e2-824d-af29449bbd56 :mtime: 20231020034437 :ctime: 20231020034435 :END: #+title: clock skew #+filetags: :public:project: * Clock Skew - Previously, you may have assumed that the system [[id:124ef912-c3fd-4fbf-98df-fc0677c8f534][clock]] signal reaches all the [[id:2c4ec126-9394-40b4-82e0-209cd3501c4b][flip-flop]]s at the same time - Owing to the physical layout of the clock wiring giving rise to different wire lengths and hence different propagation delays, in reality, the [[id:124ef912-c3fd-4fbf-98df-fc0677c8f534][clock]] edges will not arrive at the [[id:2c4ec126-9394-40b4-82e0-209cd3501c4b][flip-flop]] at the same time. This variation is known as *clock skew*. - In the following case, the clock to $FF_{1}$ ($CLK_{1}$) is in advance (by $t_{skew}$ seconds) of the clock to FF0 ($CLK_0$) * Clock skew limits clock speed the clock skew limits the maximum clock speed \[T_{C} \ge t_{pc} + t_{pd} + t_{su} + t_{skew}\]