"Digital Electronics Example Sheet I Solutions -- Atticus Kuhn"

Written By Atticus Kuhn
Tags: "project", "public"
:PROPERTIES: :ID: 4bef99d4-15dd-4bdf-8b2a-f6012cdfb5fa :mtime: 20231015052934 20231014023709 20231013055659 20231011063124 20231011042927 20231010064920 20231010022939 20231009073455 20231008084825 :ctime: 20231008084819 :END: #+title: Digital Electronics Example Sheet I Solutions -- Atticus Kuhn #+filetags: :project:public: * Example Sheet 1 These are the solutions to example sheet 1. You can find example sheet 1 at [[file:/home/atticusk/Downloads/digital_electronics_example_sheet.pdf][digital electronics example sheet 1]]. For our first supervision, lets do 1, 2, 3, 6, 8, 9, 10, 12, 13 from the worksheet. * 1. Truth Tables ** First Circuit | a | b | $\overline{a}$ | $\overline{\overline{a}.b}$ | | | x | |---+---+----------------+-----------------------------+---+---+---| | 0 | 0 | 1 | 1 | | | 0 | | 0 | 1 | 1 | 0 | | | 1 | | 1 | 0 | 0 | 1 | | | 1 | | 1 | 1 | 0 | 1 | | | 0 | So is this an XOR gate. ** Second Circuit | a | b | $\overline{a}$ | $\overline{\overline{a}+b}$ | | | x | |---+---+----------------+-----------------------------+---+---+---| | 0 | 0 | 1 | 0 | | | 1 | | 0 | 1 | 1 | 0 | | | 0 | | 1 | 0 | 0 | 1 | | | 0 | | 1 | 1 | 0 | 0 | | | 1 | So this checks boolean equality. * 2. Boolean Simplification See [[id:b4c4f83d-9d73-4a1f-9dc3-eb8ae691769e][Boolean Simplification]] for more information. ** Example 1 $a.b.c+a.b.\overline{c}=a.b.(c+\overline{c})=a.b.(1) = a.b$. ** Example 2 $a.(\overline{a} + b) = a.\overline{a} + a.b = 0 + a.b = a.b$ ** Example 3 \begin{align} (a + c).(\overline{a} + b) &= a.\overline{a}+c.\overline{a}+a.b+c.b\\ &= 0 +c.\overline{a}+a.b+c.b\\ &= c.\overline{a}+a.b+c.b\\ &= \overline{a}.c+a.b+c.b\\ &= \overline{a}.c+a.b \end{align} ** Example 4 \begin{align} (a + c).(a + d ).(b + c).(b + d ) &= =(a.a + c.a + a.d + c.d).(b.b + b.d + c.b + c.d)\\ &== (a + a.c + a.d + c.d).(b + b.d + c.b + c.d)\\ &= (a + c.d).(b + c.d)\\ &= a.b + a.c.d + b.c.d + c.d.c.d\\ &= a.b + a.c.d + b.c.d + c.d\\ &= a.b + b.c.d + c.d\\ &= a.b + c.d \end{align} * 3. Simplifying a Circuit $z= b + (\overline{a.b.c + \overline{a.a}})$ We can write $z$ as $z = b + \overline{a.b.c}.a$ See the attached image for a drawing of this new circuit. #+CAPTION: This is the simplified circuit #+NAME: fig:simplifedcircuit [[/home/atticusk/Downloads/IMG_7301.jpg]] * 6.Karnaugh Map Here is my [[id:c3126ca5-44cb-4b50-b8b1-1ce56cc50a6d][Karnaugh Map]]: | | | | | | | | | | | | | 1 | 1 | | 1 | 1 | 1 | x | So $f=a.\overline{b} + b.c$ is the simplified SOP form. * 8. Simplifying a function $f$ I will use a [[id:c3126ca5-44cb-4b50-b8b1-1ce56cc50a6d][Karnaugh Map]] in order to simplify the function $f$. Here is my Karnaugh Map. | | | | | | | 1 | 1 | 1 | | x | x | x | x | | 1 | | x | x | In SOP form: $f = b.c + b.\overline{c}.d + a.\overline{b}.\overline{c}.\overline{d}$ I will use [[id:9bfdb4ec-60e2-439d-b559-ab33fcd8e208][DeMorgan's Law]] and [[id:1fbe2347-054d-46c7-85c1-3e2e987f62ef][Product of Sums from Karnaugh Map]] in order to convert my SOP form to POS form. In POS form: $f = (a + d).(b + \overline{c} + \overline{d}).(\overline{a} + \overline{b})$ * 9. Months of the Year The months without "r" are: May, June, July, and August. In binary, this is $0101 + 0110 + 0111 + 1000$. Here is my [[id:c3126ca5-44cb-4b50-b8b1-1ce56cc50a6d][Karnaugh Map]] for the situation: | | | | | | | 1 | 1 | 1 | | | | | | | 1 | | | | By a Karnaugh Map, this is $f=\overline{A_{3}}.A_{2}.\overline{A_{1}}.A_{0} + \overline{A_{3}}.A_{2}.A_{1}.\overline{A_{0}} + \overline{A_{3}}.A_{2}.A_{1}.A_{0} + A_{3}.\overline{A_{2}}.\overline{A_{1}}.\overline{A_{0}}$ If we start from January=0000, then we get $0100 + 0101 + 0110 + 0111$. This gives use the [[id:c3126ca5-44cb-4b50-b8b1-1ce56cc50a6d][Karnaugh Map]] of | | | | | | 1 | 1 | 1 | 1 | | | | | | | | | | | which gives us the simpler expression $f = \overline{A_{3}}.A_{2}$. * 10. Timing Circuit (a) See the attached image for a timing diagram (I do not know how to draw a timing diagram inside a document). #+CAPTION: A Timing Diagram #+NAME: fig:timingdiagram [[/home/atticusk/Downloads/IMG_7302.jpg]] I drew another diagram at https://www.desmos.com/calculator/1dxhedoyog. The diagram shows that there exists a [[id:dbc98b23-847b-4dec-9959-d169d5c59ff9][static hazard]] for 1 on $z$. (b) $z = (a + \overline{c}).(b+c)$ Using [[id:9bfdb4ec-60e2-439d-b559-ab33fcd8e208][DeMorgan's Law]], we find that $\overline{z} = \overline{a}.c + \overline{b}.\overline{c}$ (c) Here is a [[id:c3126ca5-44cb-4b50-b8b1-1ce56cc50a6d][Karnaugh Map]] for the $\overline{z}$. |---+---| | 1 | | |---+---| | | | |---+---| | | 1 | |---+---| | 1 | 1 | |---+---| We can remove the static $1$ hazard if we add the term $\overline{a}.\overline{b}$. This means we can remove the static 1 hazard if we add an [[id:b00f18eb-418d-4e2f-9552-101660f6efb5][OR gate]]. See the attached image for a circuit diagram. #+CAPTION: This circuit does not have a static hazard #+NAME: fig:nohazard [[/home/atticusk/Downloads/IMG_7300.jpg]] * 12. Mutliplier using NAND Here is a multiplication table: | $A_1$ | $A_0$ | $B_1$ | $B_0$ | result | |-------+-------+-------+-------+--------| | 0 | 0 | 0 | 0 | 0000 | | 0 | 0 | 0 | 1 | 0000 | | 0 | 0 | 1 | 0 | 0000 | | 0 | 0 | 1 | 1 | 0000 | | 0 | 1 | 0 | 0 | 0000 | | 0 | 1 | 0 | 1 | 0001 | | 0 | 1 | 1 | 0 | 0010 | | 0 | 1 | 1 | 1 | 0011 | | 1 | 0 | 0 | 0 | 0000 | | 1 | 0 | 0 | 1 | 0010 | | 1 | 0 | 1 | 0 | 0100 | | 1 | 0 | 1 | 1 | 0110 | | 1 | 1 | 0 | 0 | 0000 | | 1 | 1 | 0 | 1 | 0011 | | 1 | 1 | 1 | 0 | 0110 | | 1 | 1 | 1 | 1 | 1001 | I will now draw 4 karnaugh maps. K-map for $P_3$: |---+---+---+---| | | | | | |---+---+---+---| | | | | | |---+---+---+---| | | | 1 | | |---+---+---+---| | | | | | |---+---+---+---| K-map for $P_2$: |---+---+---+---| | | | | | |---+---+---+---| | | | | | |---+---+---+---| | | | | 1 | |---+---+---+---| | | | 1 | 1 | |---+---+---+---| K-map for $P_1$: |---+---+---+---| | | | | | |---+---+---+---| | | | 1 | 1 | |---+---+---+---| | | | | 1 | |---+---+---+---| | | 1 | 1 | | |---+---+---+---| K-map for $P_0$: |---+---+---+---| | | | | | |---+---+---+---| | | 1 | 1 | | |---+---+---+---| | | 1 | 1 | | |---+---+---+---| | | | | | |---+---+---+---| This means that \[P_{3} = A_{1}.A_{0}.B_{1}.B_{0}\] \[P_{2} = A_{1}.\overline{A_{0}}.B_{1} + A_{1}.B_{1}.\overline{B_{0}}\] \[P_{1} = A_{1}.\overline{A_{0}}.B_{0} + \overline{A_{1}}.A_{0}.B_{1} + A_{0}.B_{1}.\overline{B_{0}}\] \[P_{0} = A_{0}.B_{0}\] You can see my drawing of the circuit at the attached image. #+CAPTION: This circuit multiplies numbers #+NAME: fig:multiplier [[/home/atticusk/Downloads/IMG_7299.jpg]] * 13. QM Simplification. Table 1: | group | a | b | c | d | checked? | |-------+---+---+---+---+----------| | 0 | 0 | 0 | 0 | 0 | yes | |-------+---+---+---+---+----------| | 1 | 0 | 0 | 0 | 1 | yes | | 1 | 0 | 0 | 1 | 0 | yes | | 1 | 1 | 0 | 0 | 0 | yes | |-------+---+---+---+---+----------| | 2 | 0 | 1 | 0 | 1 | yes | | 2 | 0 | 1 | 1 | 0 | yes | | 2 | 1 | 0 | 0 | 1 | yes | | 2 | 1 | 0 | 1 | 0 | yes | |-------+---+---+---+---+----------| | 3 | 0 | 1 | 1 | 1 | yes | | 3 | 1 | 1 | 1 | 0 | yes | Table 2: | group | a | b | c | d | checked? | |-------+---+---+---+---+----------| | 0 | 0 | 0 | 0 | _ | | | 0 | 0 | 0 | _ | 0 | | | 0 | - | 0 | 0 | 0 | yes | |-------+---+---+---+---+----------| | 1 | 0 | _ | 0 | 1 | | | 1 | - | 0 | 0 | 1 | yes | | 1 | - | 0 | 1 | 0 | | | 1 | 1 | 0 | _ | 0 | | | 1 | 1 | 0 | 0 | - | | | 1 | 0 | _ | 1 | 0 | | |-------+---+---+---+---+----------| | 2 | 0 | 1 | _ | 1 | | | 2 | 0 | 1 | 1 | _ | | | 2 | 1 | _ | 1 | 0 | | | 2 | _ | 1 | 1 | 0 | | Table 3: | group | a | b | c | d | checked? | |-------+---+---+---+---+----------| | 0 | - | 0 | 0 | _ | no | | 0 | - | 0 | _ | 0 | no | |-------+---+---+---+---+----------| | 1 | _ | _ | 1 | 0 | no | Prime Implicant Table: | miniterm | abcd | 0 | 1 | 2 | 5 | 6 | 7 | 8 | 9 | 10 | 14 | |-----------+------+---+---+---+---+---+---+---+---+----+----| | 1,5 | 0-01 | | X | | X | | | | | | | | 5,7 | 01-1 | | | | X | | X | | | | | | 6,7 | 011- | | | | | X | X | | | | | | 0,1,8,9 | -00- | X | X | | | | | X | X | | | | 0,2,8,10 | -0-0 | X | | X | | | | X | | X | | | 2,6,10,14 | --10 | | | X | | X | | | | X | X | By the prime implicant table, columns 9 and 14 have a single X. This means the [[id:7b635cc5-51ae-4c8d-9e18-f8a57a9718b0][Essential Prime Implicant]]s are -00- and --10. What remains is 5,7, so we can add 01-1. This means that the simplified expression is $f = \overline{b}.\overline{c} + c.\overline{d} + \overline{a}.b.d$

See Also

Boolean SimplificationKarnaugh MapKarnaugh MapDeMorgan's LawProduct of Sums from Karnaugh MapKarnaugh MapKarnaugh Mapstatic hazardDeMorgan's LawKarnaugh MapOR gateEssential Prime Implicant

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