:PROPERTIES: :ID: 894f2262-5a61-48dc-a229-4f767f68493e :mtime: 20231023030609 :ctime: 20231023030608 :END: #+title: Meta-stability in Digital Electronics #+filetags: :public:project: * [[id:6ca6a52c-d402-4b9b-a45a-892599375754][Meta-stability]] in Digital Electronics - It is not always possible to control when a [[id:2c4ec126-9394-40b4-82e0-209cd3501c4b][flip-flop]] input changes in relation to the [[id:8373651b-39e3-4772-90c3-7ac5079a1e8f][clock edge]] - For example, this can occur when the input signal comes from an external user input, e.g., a button - Consider the following example when the D input change violates the dynamic requirements - This causes the output Q to be undefined - Momentarily it can take on a voltage between 0 and $V_{DD}$ , i.e., in the invalid range * Probability of being in invalid state - Eventually, the [[id:2c4ec126-9394-40b4-82e0-209cd3501c4b][flip-flop]] output will resolve to a stable valid 0 or 1 voltage level - In theory, the resolution time is unbounded, however, we can model the probability of the resolution time, tres exceeding some particular time $t$ \[P(t_{resolution} > t) = \frac{T_{0}}{T_{c}}e^{-\frac{t}{\tau}}\] where $T_{c}$ is the clock period, and $T_0$ and $t$ are characteristics of the [[id:2c4ec126-9394-40b4-82e0-209cd3501c4b][flip-flop]]. - We can view $\frac{T_{0}}{ T_{c}}$ as the probability that the input changes at a ‘bad’ time since we see it decreases with increasing $T_c$ , and t is a time constant indicating how fast the [[id:2c4ec126-9394-40b4-82e0-209cd3501c4b][flip-flop]] will exit the metastable state * Solving using a [[id:6604ca03-a81f-44b8-9552-6ca835d23cb6][synchroniser]] We can solve using a syncrhoniser