:PROPERTIES: :ID: 73642d2d-8e68-40b5-b30f-20f8be6545e8 :mtime: 20231020033332 :ctime: 20231020033331 :END: #+title: time constrain limits clock speed #+filetags: :public:project: * Time constraint limits clock speed The time constraints of a circuit limit the maximum possible [[id:124ef912-c3fd-4fbf-98df-fc0677c8f534][clock]] speed. Let $t_{su}$ be [[id:214367a0-5fed-4959-a76b-2fc83aece21a][setup time constraint.]] Let $t_{h}$ be [[id:e873d68a-9389-4132-a8b2-f04bed7bc7fe][hold time constraint]] Let $t_{pc}$ be [[id:b50db835-9ca3-4d0d-bc41-9ea691ea3e52][Gate Propagation Delay]] from the clock. The minimum clock period is given by \[T_{C} \ge t_{pc} + t_{pd} + t_{su}\] Note that the circuit designer can usually only control the [[id:b50db835-9ca3-4d0d-bc41-9ea691ea3e52][Gate Propagation Delay]], so \[t_{pd} \le T_{C} - (t_{pc} + t_{su})\]