:PROPERTIES: :ID: e873d68a-9389-4132-a8b2-f04bed7bc7fe :mtime: 20231020033932 20231016035241 :ctime: 20231016035213 :END: #+title: hold time constraint #+filetags: :public:project: * Definition Hold time is the minimum duration that the input data must remain stable on the flip-flop input after the clock edge. * Hold time contraint $D_1$ must not change in a time shorter than $t_{hold}$ (which is the minimum flip-flip hold time). Thus, the minimum value of $t_{pc} + t_{pd}$ must be greater than $t_{hold}$. In other words \[(t_{pc} + t_{pd})min \ge t_{hold}\] * Without combinational logic - We would expect 2 flip-flops to be able to be directly cascaded i.e., with no combinational logic between them, without any timing issues. In this case, $t_{pc}= 0$, so \[t_{pd}min \ge t_{hold}\] - In other words a reliable flip-flop must have a minimum hold time shorter than the minimum propagation delay time - Often flip-flops are designed with $t_{hold} = 0$, hence the above condition is always satisfied - We will not consider hold time violations further, but note that they cannot be overcome by adjusting the clock period. Consequently, they can be hard to fix and have to be taken seriously