"Digital Electronics My Notes"

Written By Atticus Kuhn
Tags: "public", "project"
:PROPERTIES: :ID: 74aad594-77bf-4cb1-be6b-e8d3bb0011ed :mtime: 20231018025847 20231016032320 20231013030210 20231011032930 20231009031214 20231006031032 :ctime: 20231006031002 :END: #+title: Digital Electronics My Notes #+filetags: :public:project: * About This is a list of my notes related to the course [[id:95babb18-e6c9-4b1d-87e2-14ab02140571][digital electronics course]]. This should not be confused with the notes provided by the professor. Those can be found at https://www.vle.cam.ac.uk/course/view.php?id=243692 * List of Notes This is a list of all notes related to Digital Electronics - [[id:b8420d74-8ec8-48c6-b3a5-7a74375988cd][Computer architecture]] - [[id:2456deb3-bad4-4061-831f-1b7ff8d1996a][micro-architecture]] ** Logic Gates Notes - [[id:1ff18dab-36e4-42ae-80bd-1f1be4529288][Logic Variable]] - [[id:4202d577-6a6c-4c32-99af-94c045df51c7][Logic Gate]] - [[id:4e3339ac-f650-4277-95a5-51ca75b5145c][not gate]] - [[id:d96e0ef7-0b31-406b-9b5b-f3815eb697d6][AND gate]] - [[id:b00f18eb-418d-4e2f-9552-101660f6efb5][OR gate]] - [[id:0a345a91-cf81-421a-ac6b-e2a13d5c0a2a][XOR gate]] - [[id:f323676c-11c8-4783-9ea8-7eb2108c8ab2][NAND gate]] - [[id:34082fa2-800d-48a2-a9f8-3635295aa423][NOR gate]] ** Truth Tables - [[id:3033ebb1-4429-4d30-b526-24b4d2988d38][Miniterm]] - [[id:c167b95c-027b-420c-ae74-977c422c16f7][disjunctive normal form]] - [[id:1fc7095d-fca4-47f9-a474-f6deaa2471d2][Maxterm]] - [[id:44556352-e5a4-4054-afda-820829edb9d7][conjunctive normal form]] *** Simplifying Boolean Variables - [[id:c3126ca5-44cb-4b50-b8b1-1ce56cc50a6d][Karnaugh Map]] - [[id:32c7d004-ec28-4fa7-98d9-d27d653f18f7][Prime Implicant]] - [[id:7b635cc5-51ae-4c8d-9e18-f8a57a9718b0][Essential Prime Implicant]] - [[id:d7a4c921-b0c1-423c-891a-0fe87ddee4fd][Cover (Boolean Variable)]] - [[id:54cec9de-d9b0-4c78-8d59-bf75d7ebc133][Quine-McClusky Method]] ** Binary Adders - [[id:f6b359ab-b4c0-4116-b021-8553b7f8c3eb][Half Adder]] - [[id:4970a149-da47-4d9e-91cb-98be7f082be2][Full Adder]] ** Multi-level logic and hazards - [[id:c06d6ca2-11e5-413c-8ce4-0693185a6798][Multi-level Logic]] ** Clock and synchronicity - [[id:124ef912-c3fd-4fbf-98df-fc0677c8f534][computer clock]] - [[id:b22aa488-2d6d-4527-8e71-22522f68ac62][RS latch]] - [[id:e6f10291-8177-4ac3-865b-07a8d883d22c][asynchronous circuit]] - [[id:ddd7853a-3ffa-469e-bb2b-799189379141][synchronous circuit]] - [[id:ad42e3de-5877-4bc1-bf97-c016d64651f9][Transparent D Latch]]

See Also

digital electronics courseComputer architecturemicro-architectureLogic VariableLogic Gatenot gateAND gateOR gateXOR gateNAND gateNOR gateMinitermdisjunctive normal formMaxtermconjunctive normal formKarnaugh MapPrime ImplicantEssential Prime ImplicantCover (Boolean Variable)Quine-McClusky MethodHalf AdderFull AdderMulti-level Logiccomputer clockRS latchasynchronous circuitsynchronous circuitTransparent D Latch

Leave your Feedback in the Comments Section